An information processing apparatus equipped with a secure central processing unit (CPU) and a non-secure CPU to detect tampering of a program is commonly known (see, for example, Published Japanese-Translation of PCT Application, Publication No. 2009-013825). Another technology is known that in a processing apparatus, a large-scale integration (LSI) that is configured to integrate on one chip, a read only memory (ROM) such as a flash memory, a random access memory (RAM), and a processing unit, to block the reading of confidential information (secret key) of the processing apparatus itself and thereby, prevent unintended operation of the processing apparatus consequent to malice intention (see, e.g., Japanese Laid-Open Patent Publication No. H11-039158).
A configuration for a RAM to be shared between a first processor controllable by a user and a second processor not controllable by the user can be considered based on the conventional techniques. With this configuration, it can be considered that a program that is to be protected is expanded from the ROM onto the shared RAM; it is checked whether the program has been subject to tampering; if it is determined that the program is a legitimate program, the program is encrypted and transferred to another area of the shared RAM; and the second processor is caused to decrypt and execute the program.
Nonetheless, the program that is to be protected is transferred from the ROM to the RAM and is further transferred within the RAM and consequently, a problem arises in that the time consumed for starting up the program increases.